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ltm8048 1 8048fa input voltage (v) 0 v out1 current (ma) 330 230 130 280 180 80 10 20 8048 ta01b 30 51525 typical application features description 3.1v in to 32v in isolated module dc/dc converter with ldo post regulator the ltm ? 8048 is an isolated flyback module dc/dc converter with ldo post regulator. the ltm8048 has an isolation rating of 725vdc. included in the package are the switching controller, power switches, transformer, and all support components. operating over an input voltage range of 3.1v to 32v, the ltm8048 supports an output voltage range of 2.5v to 13v, set by a single resistor. there is also a linear post regulator whose output voltage is ad- justable from 1.2v to 12v as set by a single resistor. only output, input, and bypass capacitors are needed to finish the design. other components may be used to control the soft-start control and biasing. the ltm8048 is packaged in a thermally enhanced, com- pact (11.25mm 9mm 4.92mm) over-molded ball grid array (bga) package suitable for automated assembly by standard surface mount equipment. the ltm8048 is rohs compliant. l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. applications n complete switch mode power supply n 725vdc isolation n wide input voltage range: 3.1v to 32v n v out1 output: up to 440ma (v out1 = 2.5v, 24v in ) 2.5v to 13v output range n v out2 low noise linear post regulator: up to 300ma 1.2v to 12v output range n current mode control n programmable soft-start n user configurable undervoltage lockout n (e1) rohs compliant package n low profile (11.25mm 9mm 4.92mm) surface mount bga package n industrial sensors n industrial switches n ground loop mitigation total output current vs v in 725vdc isolation ltm8048 8048 ta01 v in 3.1v to 30v v out2 5v 5.7v 10f 22f 2.2f 4.7f 6.19k 162k v out1 v out2 v in run adj1 ss byp bias gnd adj2 v out C isolation barrier 725v dc isolated low noise module regulator
ltm8048 2 8048fa pin configuration absolute maximum ratings v in , run, bias ........................................................32v adj1, ss .....................................................................5v v out1 relative to v out C ............................................16v (v in C gnd) + (v out1 C v out C ) .................................36v v out2 relative to v out C ..........................................+20v adj2 relative to v out C .............................................+7v byp relative to v out C ............................................+0.6v bias above v in ........................................................ 0.1v gnd to v out C isolation (note 2) ........................ 725vdc maximum internal temperature (note 3) .............. 125c maximum solder temperature .............................. 250c storage temperature.............................. C55c to 125c (note 1) top view h g f e d c b a 1234567 bank 2 v out C bank 1 v out1 bank 4 gnd bias run adj2 byp adj1 ss bank 5 v in bank 3 v out2 bga package 45-lead (11.25mm 9mm 4.92mm) t jmax = 125c, ja = 23.2c/w, jcbottom = 5.8c/w, jctop = 23.2c/w, jb = 6.7c/w weight = 1.1g, values determined per jedec 51-9, 51-12 order information lead free finish tray part marking* package description temperature range (note 3) ltm8048ey#pbf ltm8048ey#pbf ltm8048y 45-lead (11.25mm 9mm 4.92mm) bga C40c to 125c ltm8048iy#pbf ltm8048iy#pbf ltm8048y 45-lead (11.25mm 9mm 4.92mm) bga C40c to 125c ltm8048mpy#pbf ltm8048mpy#pbf ltm8048y 45-lead (11.25mm 9mm 4.92mm) bga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltm8048 3 8048fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm8048 isolation is tested at 725vdc for one second in each polarity. note 3: the ltm8048e is guaranteed to meet performance specifications from 0c to 125c. specifications over the C40c to 125c internal temperature range are assured by design, characterization and correlation with statistical process controls. ltm8048i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, run = 12v (note 3). parameter conditions min typ max units minimum input dc voltage bias = v in l 3.1 v v out1 dc voltage r adj1 = 12.4k r adj1 = 7.15k r adj1 = 3.16k 2.5 5 12 v v v v in quiescent current v run = 0v not switching 850 1a a v out1 line regulation 6v v in 31v, i out = 0.15a 1.7 % v out1 load regulation 0.05a i out 0.2a 1.5 % v out1 ripple (rms) i out = 0.1a 20 mv input short circuit current v out1 shorted 30 ma run pin input threshold run pin rising 1.18 1.24 1.30 v run pin current v run = 1v v run = 1.3v 2.5 0.1 a a ss threshold 0.7 v ss sourcing current ss = 0v C10 a bias current v in = 12v, bias = 5v, i load1 = 100ma 8 ma minimum bias voltage (note 4) i load1 = 100ma 3.1 v ldo (v out2 ) minimum input dc voltage (note 5) 1.8 2.3 v v out2 voltage range v out1 = 16v, r adj2 open, no load (note 5) v out1 = 16v, r adj2 = 41.2k, no load (note 5) 1.22 15.8 v v adj2 pin voltage v out1 = 2v, i out2 = 1ma (note 5) v out1 = 2v, i out2 = 1ma, e- and i-grades (note 5) v out1 = 2v, i out2 = 1ma, mp-grade (note 5) l l 1.19 1.15 1.22 1.25 1.29 v v v v out2 line regulation 2v < v out1 < 16v, i out2 = 1ma (note 5) 1 5 mv v out2 load regulation v out1 = 5v, 10ma < i out2 = 300ma (note 5) 2 10 mv ldo dropout voltage i out2 = 10ma (note 5) i out2 = 100ma (note 5) i out2 = 300ma (note 5) 0.25 0.34 0.43 v v v v out2 ripple (rms) c byp = 0.01f, i out2 = 300ma, bw = 100hz to 100khz (note 5) 20 v rms range. the ltm8048mp is guaranteed to meet specifications over the full C55c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 4: this is the bias pin voltage at which the internal circuitry is powered through the bias pin and not the integrated regulator. see bias pin considerations for details. note 5: v run = 0v (flyback not running), but the v out2 post regulator is powered by applying a voltage to v out1 .
ltm8048 4 8048fa typical performance characteristics efficiency vs load efficiency vs load bias current vs v out1 load efficiency vs load efficiency vs load efficiency vs load v out1 current (ma) 0 efficiency (%) 90 70 80 60 50 100 300 8048 g01 500 200 400 12v in 24v in v out1 = 2.5v bias = 5v v out1 current (ma) 0 efficiency (%) 100 90 70 80 60 100 300 8048 g04 350 200 250 150 50 12v in 24v in v out1 = 8v bias = 5v v out1 current (ma) 0 efficiency (%) 100 90 70 80 60 100 8048 g05 250 200 150 50 12v in 24v in v out1 = 12v bias = 5v 8.5 8.0 6.0 7.0 5.0 4.0 6.5 7.5 5.5 4.5 v out1 current (ma) 0 bias current (ma) 100 300 8048 g06 500 200 400 12v in 24v in v out1 = 2.5v bias = 5v v out1 current (ma) 0 efficiency (%) 90 70 80 60 50 100 300 8048 g02 400 200 12v in 24v in v out1 = 3.3v bias = 5v v out1 current (ma) 0 efficiency (%) 90 70 80 60 50 100 300 8048 g03 350 200 250 150 50 12v in 24v in v out1 = 5v bias = 5v bias current vs v out1 load bias current vs v out1 load bias current vs v out1 load v out1 current (ma) 0 bias current (ma) 8.5 8.0 6.0 7.0 5.0 4.0 6.5 7.5 5.5 4.5 100 300 8048 g07 400 200 12v in 24v in v out1 = 3.3v bias = 5v v out1 current (ma) bias current (ma) 10 6 8 4 7 9 5 8048 g08 12v in 24v in v out1 = 5v bias = 5v 0 100 300 350 200 250 150 50 v out1 current (ma) bias current (ma) 12 11 10 6 8 4 7 9 5 8048 g09 12v in 24v in v out1 = 8v bias = 5v 0 100 300 350 200 250 150 50 unless otherwise noted, operating conditions are as in table 1 (t a = 25c).
ltm8048 5 8048fa typical performance characteristics bias current vs v out1 load maximum load vs v in maximum load vs v in 0 100 250 200 150 50 v out1 current (ma) bias current (ma) 13 12 11 10 6 8 4 7 9 5 8048 g10 12v in 24v in v out1 = 12v bias = 5v v in (v) maximum v out1 load (ma) 500 450 400 200 300 100 250 350 150 8048 g11 bias = v in if v in 5v bias = 5v if v in > 5v 010 30 20 25 15 5 2.5v out1 3.3v out1 5v out1 v in (v) maximum v out1 load (ma) 350 200 300 0 100 250 150 50 8048 12 bias = v in if v in 5v bias = 5v if v in > 5v 010 25 20 15 5 8v out1 12v out1 unless otherwise noted, operating conditions are as in table 1 (t a = 25c). minimum load vs v in minimum load vs v in input current vs v in v out1 shorted input current vs v in v out2 shorted v in (v) minimum v out1 load (ma) 40 35 30 10 20 0 15 25 5 8048 g13 010 30 20 25 15 5 2.5v out1 3.3v out1 5v out1 v in (v) input current (ma) 225 200 175 75 125 50 100 150 8048 g16 040 20 30 10 v in (v) minimum v out1 load (ma) 15 12 9 3 0 6 8048 g14 010 30 20 25 15 5 8v out1 12v out1 v in (v) input current (ma) 80 70 60 20 40 10 30 50 8048 g15 012 32 20 28 24 16 8 4 v out2 dropout voltage vs load v out2 load current (ma) v out2 dropout voltage (mv) 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 8048 g17 0 100 300 200 250 150 50 C40c 125c 25c v out2 = 3.3v v out2 output ripple and noise 500v/div 8048 g26 1s/div measured per an70, using hp461a amplifier, 150mhz bw
ltm8048 6 8048fa junction temperature rise vs load current v out2 load current (ma) temperature rise (c) 10 9 8 4 6 0 5 7 2 3 1 80 4 8 g 1 8 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 1.2v typical performance characteristics junction temperature rise vs load current junction temperature rise vs load current junction temperature rise vs load current junction temperature rise vs load current junction temperature rise vs load current v out2 load current (ma) temperature rise (c) 10 9 8 4 6 0 5 7 2 3 1 8048 g19 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 1.5v v out2 load current (ma) temperature rise (c) 12 10 8 4 6 0 2 8048 g22 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 3.3v v out2 load current (ma) temperature rise (c) 10 9 8 4 6 0 5 7 2 3 1 8048 g20 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 1.8v v out2 load current (ma) temperature rise (c) 14 12 10 8 4 6 0 2 8048 g23 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 5v v out2 load current (ma) temperature rise (c) 10 9 8 4 6 0 5 7 2 3 1 8048 g21 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 2.5v unless otherwise noted, operating conditions are as in table 1 (t a = 25c).
ltm8048 7 8048fa typical performance characteristics junction temperature rise vs load current junction temperature rise vs load current v out2 load current (ma) temperature rise (c) 16 14 12 10 8 4 6 0 2 8048 g24 0 100 300 200 250 150 50 3.3v in 5v in 12v in 24v in v out2 = 8v v out2 load current (ma) temperature rise (c) 16 14 12 10 8 4 6 0 2 8048 g25 0 100 250 200 150 50 3.3v in 5v in 12v in 24v in v out2 = 12v unless otherwise noted, operating conditions are as in table 1 (t a = 25c).
ltm8048 8 8048fa pin functions v out1 (bank 1): v out1 and v out C comprise the isolated output of the ltm8048 flyback stage. apply an external capacitor between v out1 and v out C . do not allow v out C to exceed v out1 . v out C (bank 2): v out C is the return for both v out1 and v out2 . v out1 and v out C comprise the isolated output of the ltm8048. in most applications, the bulk of the heat flow out of the ltm8048 is through the gnd and v out C pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. apply an external capacitor between v out1 and v out C . v out2 (bank 3): the output of the secondary side linear post regulator. apply the load and output capacitor between v out2 and v out C . see the applications information section for more information on output capacitance and reverse output characteristics. gnd (bank 4): this is the primary side local ground of the ltm8048 primary. in most applications, the bulk of the heat flow out of the ltm8048 is through the gnd and v out C pads, so the printed circuit design has a large impact on the thermal performance of the part. see the pcb layout and thermal considerations sections for more details. v in (bank 5): v in supplies current to the ltm8048s inter- nal regulator and to the integrated power switch. these pins must be locally bypassed with an external, low esr capacitor. adj2 (pin a2): this is the input to the error amplifier of the secondary side ldo post regulator. this pin is internally clamped to 7v. the adj2 pin voltage is 1.22v referenced to v out C and the output voltage range is 1.22v to 12v. ap- ply a resistor from this pin to v out C , using the equation r adj2 = 608.78/(v out2 C 1.22)k. if the post regulator is not used, leave this pin floating. byp (pin b2): the byp pin is used to bypass the refer- ence of the ldo to achieve low noise performance from the linear post regulator. the byp pin is clamped internally to 0.6v relative to v out C . a small capacitor from v out2 to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01f can be used for reducing output voltage noise to a typical 20v rms over a 100hz to 100khz bandwidth. if not used, this pin must be left unconnected. run (pin f3): a resistive divider connected to v in and this pin programs the minimum voltage at which the ltm8048 will operate. below 1.24v, the ltm8048 does not deliver power to the secondary. above 1.24v, power will be de- livered to the secondary and 10a will be fed into the ss pin. when run is less than 1.24v, the pin draws 2.5a, allowing for a programmable hysteresis. do not allow a negative voltage (relative to gnd) on this pin. adj1 (pins g7): apply a resistor from this pin to gnd to set the output voltage v out1 relative to v out C , using the recommended value given in table 1. if table 1 does not list the desired v out1 value, the equation r adj1 = 28.4 v out1 ?0.879 () k may be used to approximate the value. to the seasoned designer, this exponential equation may seem unusual. the equation is exponential due to non-linear current sources that are used to temperature compensate the regulation. bias (pin h5): this pin supplies the power necessary to operate the ltm8048. it must be locally bypassed with a low esr capacitor of at least 4.7f. do not allow this pin voltage to rise above v in . ss (pin h6): place a soft-start capacitor here to limit inrush current and the output voltage ramp rate. do not allow a negative voltage (relative to gnd) on this pin.
ltm8048 9 8048fa block diagram v in run adj1 *do not allow bias voltage to be above v in gnd 0.1f 1f 499k v out2 v out1 adj2 current mode controller low noise ldo v out C byp ss bias* 8048 bd t t
ltm8048 10 8048fa operation the ltm8048 is a stand-alone isolated flyback switching dc/dc power supply that can deliver up to 440ma of output current. this module provides a regulated output voltage programmable via one external resistor from 2.5v to 13v. it is also equipped with a high performance linear post regulator. the input voltage range of the ltm8048 is 3.1v to 32v. given that the ltm8048 is a flyback converter, the output current depends upon the input and output voltages, so make sure that the input voltage is high enough to support the desired output voltage and load current. the typical performance characteristics section gives several graphs of the maximum load versus v in for several output voltages. a simplified block diagram is given. the ltm8048 contains a current mode controller, power switching element, power transformer, power schottky diode, a modest amount of input and output capacitance and a high performance linear post regulator. the ltm8048 has a galvanic primary to secondary isola- tion rating of 725vdc. this is verified by applying 725vdc between the primary to secondary for 1 second and then applying C725vdc for 1 second. for details please refer to the isolation and working voltage section. an internal regulator provides power to the control cir- cuitry. the bias regulator normally draws power from the v in pin, but if the bias pin is connected to an external voltage higher than 3.1v, bias power will be drawn from the external source, improving efficiency. v bias must not exceed v in . the run pin is used to turn on or off the ltm8048, disconnecting the output and reducing the input current to 1a or less. the ltm8048 is a variable frequency device. for a fixed input and output voltage, the frequency increases as the load increases. for light loads, the current through the internal transformer may be discontinuous. the post regulator is a high performance 300ma low dropout regulator with micropower quiescent current and shutdown. the device is capable of supplying 300ma at a dropout voltage of 300mv. output voltage noise can be lowered to 20v rms over a 100hz to 100khz bandwidth with the addition of a 0.01f reference bypass capacitor. additionally, this reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. the linear regulator is protected against both reverse input and reverse output voltages.
ltm8048 11 8048fa applications information for most applications, the design process is straight forward, summarized as follows: 1. look at table 1a (or table 1b, if the post linear regula- tor is used) and find the row that has the desired input range and output voltage. 2. apply the recommended c in , c out1 , c out2 , r adj1 , r adj2 and c byp if required. 3. connect bias as indicated, or tie to an external source up to 15v or v in , whichever is less. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. bear in mind that the maximum output current may be limited by junction temperature, the relationship between the input and output voltage magnitude and polarity and other factors. please refer to the graphs in the typical performance characteristics section for guidance. capacitor selection considerations the c in , c out1 and c out2 capacitor values in table 1 are the minimum recommended values for the associated op- erating conditions. applying capacitor values below those indicated in table 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. again, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and ap- plied voltage and give dependable service. other types, including y5v and z5u have very large temperature and voltage coefficients of capacitance. in an application cir- cuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8048. a ceramic input capacitor combined with trace or cable inductance forms a high-q (underdamped) tank circuit. if the ltm8048 circuit is plugged into a live supply, the input voltage can ring to much higher than its nominal value, possibly exceeding the devices rating. this situation is easily avoided; see the hot-plugging safely section. ltm8048 table 1a. recommended component values and configuration for specific v out1 voltages (t a = 25c) v in v out1 v bias c in c out1 r adj1 3.1v to 32v 2.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 12.4k 3.1v to 32v 3.3v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10k 3.1v to 29v 5v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 16v, 1210 7.15k 3.1v to 26v 8v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 10v, 1206 4.53k 3.1v to 24v 12v 3.1v to 15v or open 2.2f, 25v, 0805 10f, 16v, 1210 3.16k 9v to 15v 2.5v v in 2.2f, 50v, 1206 100f, 6.3v, 1210 12.4k 9v to 15v 3.3v v in 2.2f, 50v, 1206 47f, 6.3v, 1210 10k 9v to 15v 5v v in 2.2f, 50v, 1206 22f, 16v, 1210 7.15k 9v to 15v 8v v in 2.2f, 50v, 1206 22f, 10v, 1206 4.53k 9v to 15v 12v v in 2.2f, 25v, 0805 10f, 16v, 1210 3.16k 18v to 32v 2.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 12.4k 18v to 32v 3.3v 3.1v to 15v or open 2.2f, 50v, 1206 47f, 6.3v, 1210 10k 18v to 29v 5v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 16v, 1210 7.15k 18v to 26v 8v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 10v, 1206 4.53k 18v to 24v 12v 3.1v to 15v or open 2.2f, 50v, 1206 10f, 16v, 1210 3.16k note: do not allow bias to exceed v in , a bulk input capacitor is required.
ltm8048 12 8048fa ltm8048 table 1b. recommended component values and configuration for specific v out2 voltages (t a = 25c) v in v out1 v out2 v bias c in c out1 c out2 r adj1 r adj2 3.1v to 32v 1.71v 1.2v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 16.5k open 3.1v to 32v 2.02v 1.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 14.7k 2.32m 3.1v to 32v 2.34v 1.8v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 13.3k 1.07m 3.1v to 32v 3.08v 2.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 10.5k 487k 3.1v to 32v 3.92v 3.3v 3.1v to 15v or open 2.2f, 50v, 1206 47f, 6.3v, 1210 10f, 6.3v, 1206 8.66k 294k 3.1v to 29v 5.7v 5v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 16v, 1210 10f, 6.3v, 1206 6.19k 162k 3.1v to 26v 8.85v 8v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 10v, 1206 10f, 10v, 1206 4.12k 88.7k 3.1v to 21v 13v 12v 3.1v to 15v or open 2.2f, 25v, 0805 10f, 16v, 1210 10f, 16v, 1206 2.94k 56.2k 9v to 15v 1.71v 1.2v v in 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 16.5k open 9v to 15v 2.02v 1.5v v in 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 14.7k 2.32m 9v to 15v 2.34v 1.8v v in 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 13.3k 1.07m 9v to 15v 3.08v 2.5v v in 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 10.5k 487k 9v to 15v 3.92v 3.3v v in 2.2f, 50v, 1206 47f, 6.3v, 1210 10f, 6.3v, 1206 8.66k 294k 9v to 15v 5.7v 5v v in 2.2f, 50v, 1206 22f, 16v, 1210 10f, 6.3v, 1206 6.19k 162k 9v to 15v 8.85v 8v v in 2.2f, 50v, 1206 22f, 10v, 1206 10f, 10v, 1206 4.12k 88.7k 9v to 15v 13v 12v v in 2.2f, 25v, 0805 10f, 16v, 1210 10f, 16v, 1206 2.94k 56.2k 18v to 32v 1.71v 1.2v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 16.5k open 18v to 32v 2.02v 1.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 14.7k 2.32m 18v to 32v 2.34v 1.8v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 13.3k 1.07m 18v to 32v 3.08v 2.5v 3.1v to 15v or open 2.2f, 50v, 1206 100f, 6.3v, 1210 10f, 6.3v, 1206 10.5k 487k 18v to 32v 3.92v 3.3v 3.1v to 15v or open 2.2f, 50v, 1206 47f, 6.3v, 1210 10f, 6.3v, 1206 8.66k 294k 18v to 29v 5.7v 5v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 16v, 1210 10f, 6.3v, 1206 6.19k 162k 18v to 26v 8.85v 8v 3.1v to 15v or open 2.2f, 50v, 1206 22f, 10v, 1206 10f, 10v, 1206 4.12k 88.7k note: do not allow bias to exceed v in , a bulk input capacitor is required. applications information bias pin considerations the bias pin is the output of an internal linear regulator that powers the ltm8048s internal circuitry. it is set to 3v and must be decoupled with a low esr capacitor of at least 4.7f. the ltm8048 will run properly without apply- ing a voltage to this pin, but will operate more efficiently and dissipate less power if a voltage greater than 3.1v is applied. at low v in , the ltm8048 will be able to deliver more output current if bias is 3.1v or greater. up to 32v may be applied to this pin, but a high bias voltage will cause excessive power dissipation in the internal circuitry. for applications with an input voltage less than 15v, the bias pin is typically connected directly to the v in pin. for input voltages greater than 15v, it is preferred to leave the bias pin separate from the v in pin, either powered from a separate voltage source or left running from the internal regulator. this has the added advantage of keeping the physical size of the bias capacitor small. do not allow bias to rise above v in . soft-start for many applications, it is necessary to minimize the inrush current at start-up. the built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot by applying a capacitor from ss to gnd. when the ltm8048 is enabled, whether from v in reaching a sufficiently high voltage or run being pulled high, the ltm8048 will source approximately 10a out of the ss pin. as this current gradually charges the capacitor from ss to gnd, the ltm8048 will correspondingly increase the power delivered to the output, allowing for a graceful turn-on ramp.
ltm8048 13 8048fa applications information isolation and working voltage the ltm8048 isolation is tested by tying all of the primary pins together, all of the secondary pins together and subjecting the two resultant circuits to a differential of 725vdc for one second. this establishes the isolation voltage rating, but it does not determine the working volt- age rating, which is subject to the application board layout and possibly other factors. the metal to metal separation of the primary and secondary throughout the ltm8048 substrate is 0.44mm. v out2 post regulator v out2 is produced by a high performance low dropout 300ma regulator. at full load, its dropout is less than 430mv over temperature. its output is set by applying a resistor from the r adj2 pin to gnd; the value of r adj2 can be calculated by the equation: r adj2 = 608.78 v out2 ? 1.22 k v out1 to v out C reverse voltage the ltm8048 cannot tolerate a reverse voltage from v out1 to v out C during operation. if v out C raises above v out1 during operation, the ltm8048 may be damaged. to protect against this condition, a low forward drop power schottky diode has been integrated into the ltm8048, anti-parallel to v out1 /v out C . this can protect the output against many reverse voltage faults. reverse voltage faults can be both steady state and transient. an example of a steady state voltage reversal is accidentally misconnecting a powered ltm8048 to a negative voltage source. an example of transient voltage reversals is a momentary connection to a negative voltage. it is also possible to achieve a v out1 reversal if the load is short-circuited through a long cable. the inductance of the long cable forms an lc tank circuit with the v out1 capacitance, which drive v out1 negative. avoid these conditions. v out2 post regulator bypass capacitance and low noise performance the v out2 linear regulator may be used with the addition of a 0.01f bypass capacitor from v out to the byp pin to lower output voltage noise. a good quality low leakage capacitor, such as a x5r or x75 ceramic, is recommended. this capacitor will bypass the reference of the regulator, lowering the output voltage noise to as low as 20v rms . using a bypass capacitor has the added benefit of improv- ing transient response. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8048. the ltm8048 is neverthe- less a switching power supply, and care must be taken to minimize electrical noise to ensure proper operation. even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. see figure 1 for a suggested layout. ensure that the grounding and heat sinking are acceptable. figure 1. layout showing suggested external components, planes and thermal vias 8048 f01 bias run gnd adj2 byp adj1 ltm8048 ss c out2 c out1 v out C v out2 v in v out1 c in thermal/interconnect vias
ltm8048 14 8048fa applications information a few rules to keep in mind are: 1. place the r adj1 and r adj2 resistors as close as possible to their respective pins. 2. place the c in capacitor as close as possible to the v in and gnd connections of the ltm8048. 3. place the c out1 capacitor as close as possible to v out1 and v out C . likewise, place the c out2 capacitor as close as possible to v out2 and v out C . 4. place the c in and c out capacitors such that their ground current flow directly adjacent or underneath the ltm8048. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8048. 6. use vias to connect the gnd copper area to the boards internal ground planes. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. pay attention to the location and density of the thermal vias in figure 1. the ltm8048 can benefit from the heat sinking afforded by vias that connect to internal gnd planes at these locations, due to their proximity to internal power handling components. the optimum number of thermal vias depends upon the printed circuit board design. for example, a board might use very small via holes. it should employ more thermal vias than a board that uses larger holes. hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of the ltm8048. however, these capaci- tors can cause problems if the ltm8048 is plugged into a live supply (see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the volt- age at the v in pin of the ltm8048 can ring to more than twice the nominal input voltage, possibly exceeding the ltm8048s rating and damaging the part. a similar phe- nomenon can occur inside the ltm8048 module, at the output of the integrated emi filter, with the same potential of damaging the part. if the input supply is poorly con- trolled or the user will be plugging the ltm8048 into an energized supply, the input network should be designed to prevent this overshoot. this can be accomplished by installing a small resistor in series to v in , but the most popular method of controlling input voltage overshoot is adding an electrolytic bulk capacitor to the v in or f in net. this capacitors relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filter- ing and can slightly improve the efficiency of the circuit, though it can be a large component in the circuit. thermal considerations the ltm8048 output current may need to be derated if it is required to operate in a high ambient temperature. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the temperature rise curves given in the typical performance characteristics section can be used as a guide. these curves were generated by the ltm8048 mounted to a 58cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. for increased accuracy and fidelity to the actual application, many designers use fea to predict thermal performance. to that end, the pin configuration section of the data sheet typically gives four thermal coefficients: ja : thermal resistance from junction to ambient jcbottom : thermal resistance from junction to the bot- tom of the product case jctop : thermal resistance from junction to top of the product case jcboard : thermal resistance from junction to the printed circuit board. while the meaning of each of these coefficients may seem to be intuitive, jedec has defined each to avoid confu- sion and inconsistency. these definitions are given in jesd 51-12, and are quoted or paraphrased as follows:
ltm8048 15 8048fa applications information ja is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. jcbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module converter, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient envi- ronment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. jctop is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module converter are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junc- tion to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. jcboard is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module converter and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two-sided, two-layer board. this board is described in jesd 51-9. given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a module converter. thus, none of them can be individually used to accurately predict the thermal performance of the product. likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the products data sheet. the only appropriate way to use the coefficients is when running a detailed thermal analysis, such as fea, which considers all of the thermal resistances simultaneously. a graphical representation of these thermal resistances is given in figure 2. the blue resistances are contained within the module converter, and the green are outside. the die temperature of the ltm8048 must be lower than the maximum rating of 125c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8048. the bulk of the heat flow out of the ltm8048 is through the bottom of the module and the bga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, result- ing in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. figure 2. 8048 f02 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance
ltm8048 16 8048fa typical applications 12v flyback converter with low noise bypass 3.3v and 2.5v flyback converter ltm8048 8048 ta04 v in 3.5vdc to 32vdc v out2 2.5v v out1 3.3v 10k 487k 4.7f v out1 v out2 v in run adj1 ss byp bias gnd adj2 v out C isolation barrier 725vdc isolation 10f 100f 2.2f 725vdc isolation ltm8048 8048 ta03 v in 5vdc to 23vdc v out2 12v 2.94k 56.2k 4.7f v out1 v out2 v in run adj1 ss byp bias gnd adj2 v out C 0.01f isolation barrier 13v 10f 10f 5v 3.3v flyback converter v out2 output current vs v in v out2 output current vs v in total output current vs v in 725vdc isolation ltm8048 8048 ta02 v in 9v to 15v v out2 3.3v 8.66k 294k 4.7f v out1 v out2 v in run adj1 ss byp bias gnd adj2 v out C isolation barrier 3.9v 10f 47f 2.2f v in (v) 9 output current (ma) 340 320 300 260 220 280 240 200 11 13 8048 ta02b 15 10 12 14 v in (v) 5 output current (ma) 250 230 210 190 170 150 110 70 130 90 50 15 8048 ta03b 25 10 20 v in (v) 0 output current (ma) 500 450 400 350 250 150 300 200 100 16 8048 ta04b 32 824
ltm8048 17 8048fa pin function pin function pin function pin function pin function pin function pin function pin function a1 v out2 b1 v out2 c1 - d1 - e1 gnd f1 - g1 v in h1 v in a2 adj2 b2 byp c2 - d2 - e2 gnd f2 - g2 v in h2 v in a3 v out C b3 v out C c3 - d3 - e3 gnd f3 run g3 - h3 - a4 v out C b4 v out C c4 - d4 - e4 gnd f4 gnd g4 gnd h4 gnd a5 v out C b5 v out C c5 - d5 - e5 gnd f5 gnd g5 gnd h5 bias a6 v out1 b6 v out1 c6 - d6 - e6 gnd f6 gnd g6 gnd h6 ss a7 v out1 b7 v out1 c7 - d7 - e7 gnd f7 gnd g7 adj1 h7 gnd pin assignment table (arranged by pin number) package description package photo
ltm8048 18 8048fa package top view 4 pin a1 corner y x aaa z aaa z detail a package bottom view 3 see notes h g f e d c b a 1 2 3 4 5 6 7 pin 1 bga 45 0510 rev ? tray pin 1 bevel package in tray loading orientation component pin a1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (45 places) detail b substrate 0.27 C 0.37 3.95 C 4.05 // bbb z a a1 b1 ccc z detail b package side view mold cap z m xy z ddd m z eee symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.71 0.60 nom 4.92 0.60 4.32 0.78 0.63 11.25 9.0 1.27 8.89 7.62 max 5.12 0.70 4.42 0.85 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 45 a2 d e e b f g suggested pcb layout top view 0.000 0.635 1.905 0.635 3.175 1.905 4.445 3.175 4.445 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 4.1275 4.7625 ltmxxxxxx module package description bga package 45-lead (11.25mm 9.00mm 4.92mm) (reference ltc dwg # 05-08-1869 rev ?) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltm8048 19 8048fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 6/12 added storage temperature range clarify v out2 and adj1 pin function description clarify r adj2 equation updated related parts table 2 8 13 20
ltm8048 20 8048fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0612 rev a ? printed in usa related parts typical application 5v flyback converter with low noise bypass 725vdc isolation ltm8048 8048 ta05 v in 15vdc to 30vdc v out2 5v 6.19k 162k 4.7f v out1 v out2 v in run adj1 ss byp bias gnd adj2 v out C 0.01f isolation barrier 5.7v 10f 22f 2.2f total output current vs v in v in (v) 15 output current (ma) 400 380 360 340 320 300 260 220 280 240 200 8048 ta05b 30 25 20 part number description comments ltm8031 ultralow emi 1a module regulator en55022 class b compliant, 3.6v v in 36v; 0.8v v out 10v ltm8032 ultralow emi 2a module regulator en55022 class b compliant, 3.6v v in 36v; 0.8v v out 10v ltm8033 ultralow emi 3a module regulator en55022 class b compliant, 3.6v v in 36v; 0.8v v out 24v ltm4612 ultralow emi 5a module regulator en55022 class b compliant, 5v v in 36v; 3.3v v out 15v ltm8061 li-ion/polymer module battery charger 4.95v v in 32v, 2a charge current, 1-cell and 2-cell, 4.1v or 4.2v per cell ltm4613 ultralow emi 8a module regulator en55022 class b compliant, 5v v in 36v; 3.3v v out 15v LTM8047 725vdc isolated module converter 3.1v v in 32v; 2.5v v out 12v

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